In contemporary microprocessors, the size of on-die Static Random Access Memory (SRAM) cache almost doubles every generation. This is largely enabled by technology feature scaling which allows more device integration from one process to the next. As feature length scales, both gate oxide thickness and threshold voltage scale too. This considerably increases gate-oxide and sub-threshold leakage currents, respectively. Larger leakage power is a major concern for mobile and reliable operation. In general, a hefty portion of a microprocessor's total active leakage power is consumed by SRAM cache. This is because on chip SRAM (with millions of cells) is at any given cycle in a “stand-by” state. This means that the SRAM is basically doing nothing except preserving stored data. Upon access, only one row in a given memory bank is activated (either being read or written).
With the partitioning of the SRAM into a larger number of small memory banks, aggressive power management techniques can be employed by collapsing the power supply of unselected memory banks. These techniques leverage the higher intrinsic stability of the SRAM cell when it is unselected. The intrinsic stability of the SRAM cell corresponds to the noise-margin of the cross-coupled inverter loop of the cell when it is disconnected from the bit-lines. In contrast, the read stability of the SRAM cell corresponds to the noise-margin of the inverter loop with the word-line being active and the cell internal nodes being connected to the bit-lines. The read instability is usually worse than the intrinsic stability. Consequently the power supply can be dropped to a far lower value than is the case with the cell being read-out. Powering down the supply may be accomplished by the use of “sleep switches” which are deactivated when cells are idled and activated when the cells are being written or read out.
Standby leakage current is the current which may flow through a logic circuit when a transistor within the circuit is at high impedance and attempting to hold an output voltage at a certain level. Standby leakage current can cause a loss of the signal output and can also increase power consumption of the logic circuit. There is therefore a need to reduce standby leakage current and power consumption of logic circuits.